The present invention relates generally to semiconductor devices and IC chips including the semiconductor devices. More particularly, the invention relates to semiconductor devices having a thin polycrystalline silicon film active layer in which conduction channels of the devices are formed.
Polycrystalline silicon active layers are known to have a higher effective carrier mobility than amorphous silicon layers. In addition, since polycrystalline silicon has greater thermal stability, high temperature processes may be employed for MOS TFT fabrication. Therefore, polycrystalline silicon is considered to be more advantageous than amorphous silicon for use in thin film semiconductor devices. However, on the other hand, polycrystalline silicon has the drawback of charge carrier traps along grain boundaries which results in a relatively high threshold voltage and a relatively high gate voltage required for operation of the finished MOS TFT.
In order to reduce trap density in the polycrystalline silicon layer, conventional MOS TFT's are annealed with hydrogen plasma following fabrication. This conventional process for reducing the trap density requires a relatively long annealing process. This reduces the overall production yield. Furthermore, the plasma itself tends to damage the MOS TFT. In addition, MOS TFT's are normally subjected to bias temperature treatment tests and so forth, during which hydrogen retained in traps in the polycrystalline silicon layer tends to be released by the traps and escape from the silicon layer. As a result, the trap density increases again and degrades the MOS TFT performance.